1. Field of the Invention
The present invention relates to display panel driving methods, display panel drivers, and display panel driving programs. Particularly, the present invention relates to driving techniques for time-divisionally driving two or more signal lines (data lines) within a display panel with a single amplifier.
2. Description of the Related Art
As display panels have been shifted to higher resolution, signal lines (or data lines) within display panels are significantly increased in the number, and thus the intervals between adjacent signal lines are significantly decreased. One issue caused by the increase in the number of the signal lines is difficulty in providing electrical connections between the signal lines and the display panel driver; the decrease in the intervals between adjacent signal lines undesirably makes it difficult to provide sufficient spacing between external wirings connected between the signal lines and the display panel driver. Another issue is the increase in the number of amplifiers for driving the signal lines incorporated within the driver. The increased number of amplifiers undesirably increases the size of the driver, and thus increases the cost.
One approach for overcoming the above described issues is a time-divisional drive technique, which involves driving two or more signal lines within a display panel with a single amplifier in a time divisional manner. Japanese Laid-Open Patent Application No. H04-52684A, for example, discloses one of such techniques where three signal lines are selectively conducted by the action of three switching elements mounted on a liquid crystal display panel for operation in a time division mode.
FIG. 1 is a block diagram of a display device employing the technique disclosed in this document. The display device is designed to drive three signal lines with a single amplifier in a time-divisional manner.
Specifically, the display device is composed of a liquid crystal panel 10 and a driver 20. The liquid crystal panel 10 includes a set of signal lines DR, DG, and DB, associated with red (R), green (G), and blue (B), respectively, and a set of scanning (gate) lines G1, G2, . . . GM (M being a natural number equal to or more than two). The signal lines DR, DG, and DB may be collectively referred to as signal lines D, hereinafter, when they need not to be discriminated. There is provided an R pixel CiR at the intersection of the signal line DR and the scanning (gate) line Gi. Correspondingly, provided are a G pixel CiG associated with green at the intersection of the signal line DG and the scanning (gate) line Gi, and a B pixel CiB at the intersection of the signal line DB and the scanning (gate) line Gi. The R pixel CiR, the G pixel CiG, and the B pixel CiB, which are aligned in the horizontal along the scanning line Gi, construct a pixel set Pi, which functions as a dot representing color within the liquid crystal panel 10.
Each pixel includes a TFT (thin film transistor) 11 and a liquid crystal capacitor 12. The liquid crystal capacitor 12 is composed of a pixel electrode 12a and a common electrode 12b, filled with liquid crystal material therebetween. The sources of the TFTs 11 within the R pixel CiR, the G pixel CiG, and the B pixel CiB are connected to the associated signal lines DR, DG, and DB, and the gates of the TFTs 11 are commonly connected to the scanning line Gj. The drains of the TFTs 11 are connected to the pixel electrodes 12a of the liquid crystal capacitors 12.
The signal lines DR, DG, and DB are connected to input terminals 14 via switches 13R, 13G, and 13B, respectively. The switches 13R, 13G, and 13B are composed of TFTs integrated within the liquid crystal panel 10. The switches 13R, 13G, and 13B are turned on and off in response to control signals S1, S2, and S3 received from the driver 20, respectively. The input terminals 14 receive drive voltages from the driver 20 for driving the associated pixels. As described later in more detail, the drive voltages used for driving the R pixel CiR, the G pixel CiG, and the B pixel CiB are sequentially supplied to the input terminals 14; with the switches 13R, 13G, and 13B turned on and off exclusively, the drive voltages are serially supplied in a sequence to the signal lines DR, DG, and DB for selectively driving the R pixel CiR, the G pixel CiG, and the B pixel CiB. The switches 13R, 13G, and 13B may be collectively referred to as switches 13, hereinafter, for ease of the description.
The driver 20 includes a shift register 21, a data register 22, a latch circuit 23, a D/A converter 24, and a set of amplifiers 25. The shift register 21 shifts an input clock signal CLK therein for generating shifted pulses. The data register 22 is triggered with the shifted pulses to latch the data signal and for providing a series of RGB data indicative of the graylevel of each pixel. The latch circuit 23 latches the RGB data received from the data register 22, and provides the D/A converter 24 with the latched RGB data. In response to the RGB data received from the latch circuit 23, the D/A converter 24 selects and supplies a set of desired grayscale voltages to the amplifiers 25. The grayscale voltages received from the D/A converter 24 are then amplified and transferred by the amplifiers 25 to the input terminals 14 of the liquid crystal panel 10.
The driver 20 additionally includes a control circuit 26 for generating the control signals S1, S2, and S3. The control signals S1, S2, and S3 are forwarded to the respective switches 13 to select the switches 13. The control circuit 26 provides a timing control for synchronizing the control signals S1, S2, and S3 with the timing of supplying the drive voltages from the amplifiers 25 to the input terminals 14. The timing control by the control circuit 26 allows the switches 13 to be turned on and off as timed with the drive voltages being received by the input terminals 14 and delivered to the desired signal lines. The timing control of the control circuit 26 is conducted in accordance with a program stored in a storage device of the driver 20 (not shown).
Driving a set of the R pixel CnR, the G pixel CnG, and the B pixel CnB along an nth line is achieved through the following sequence.
At first, the nth scanning line Gn, connected to the R pixel CnR, the G pixel CnG, and the B pixel CnB, is activated to turn on the TFTs 11 within the R pixel CnR, the G pixel CnG, and the B pixel CnB. This allows the R pixel CnR, the G pixel CnG, and the B pixel CnB to be ready to receive the drive voltages.
The drive voltage to be supplied to the R pixel CnR is then provided from the associated amplifier 25 to the associated input terminal 14. In synchronization of the provision of the drive voltage, the signal line DR is selected; more specifically, the switch 13R is turned on with the other switches 13G and 13B turned off. As a result, the signal line DR is connected to the input terminal 14 while the other signal lines DG and DB are placed into the high-impedance state, disconnected from the input terminal 14. This allows the drive voltage to be transferred along the signal line DR to the R pixel CnR. This achieves charging the liquid crystal capacitor 12 within the R pixel CnR with the drive voltage.
Then, the drive voltage to be supplied to the G pixel CnG is provided from the amplifier 25 to the input terminal 14. In synchronization with the provision of the drive voltage, the signal line DG is selected. This allows the drive voltage to be transferred along the signal line DG and received by the G pixel CnG.
Correspondingly, the drive voltage to be supplied to the B pixel CnB is provided from the amplifier 25 to the input terminal 14. In synchronization with the provision of the drive voltage, the signal line DB is selected. This allows the drive voltage to be transferred along the signal line DB and received by the B pixel CnB.
As described above, the signal lines DR, DG, and DB are time-divisionally driven by the amplifier 25, and the drive voltages are written into the R pixel CnR, the G pixel CnG, and the B pixel CnB in this order.
The aforementioned Japanese Laid-Open Patent application discloses that signal lines may not be associated with R, G, and B colors, and that the number of signal lines driven with a single amplifier may be two or four or more. Japanese Laid-Open Patent Application No. P2001-109435A, for example, discloses a technique for switching two signal lines with a selector circuit within a display panel. Additionally, Japanese Laid-Open Patent Application No. P2001-337657A discloses a technique for switching six signal lines with six analog switches.
The two known techniques, however, have a drawback that the drive voltage developed across the liquid crystal capacitor 12 within each pixel may be varied from the desired level after the associated signal line is placed into the high-impedance state, disconnected from the associated input terminal 14.
The variation in the drive voltage may result from three major causes. The first cause is leakage through TFTs within the switches 13 provided for switching the signal lines D. Referring to FIG. 1, the signal lines D are inevitably long, and thus have increased capacitance. This requires the TFTs within the switches 13 to have increased drive ability for driving the signal lines D. Accordingly, the TFTs are designed to have an increased gate width and reduced gate length, and a small on-resistance; however, such designed TFTs suffer from increased leakage. Therefore, charges accumulated at the pixel electrodes 12a are discharged through the TFTs within the switches 13 hence declining the drive voltages from the desired levels. Such leakage is enhanced as the difference between the drive voltages to be supplied to the adjacent signal lines is increased.
The second cause is capacitance coupling between the signal lines. When the signal line DG is driven with a drive voltage after the adjacent signal line DR is placed into the high-impedance state, for example, the voltage on the signal line DR is varied by the effect of capacitance coupling between the two signal lines DR and DG. Such variation in the voltage at the signal line DR will result in a change in the drive voltage across the pixel.
The third cause is delay of the rise (or the fall) of a common voltage VCOM developed on the common electrode 12b. In AC driving, the common voltage VCOM is inverted before the drive voltage is fed to the pixel. During the pixels being driven with the associated drive voltages, the common voltage VCOM should remain stable. As the common electrode 12b has a large size, the duration required for driving the common electrode 12b is inevitably prolonged. As a result, the common voltage VCOM may be varied during the drive of the pixels. Such variation thus causes a change in the drive voltages from the desired levels. Pixels driven at the earlier stage experience increased change in the drive voltages.
The changes in the drive voltages will be perceived as uneven brightness by the user of the liquid crystal penal 10. More particularly, the changes in the drive voltages appear as vertical segments of uneven brightness (along the signal lines D1 to D3).
The increase in the number of the signal lines for each amplifier undesirably causes increased change in the drive voltages. The changes in the drive voltages is thus emphasized as one of the most critical drawbacks of recent liquid crystal panels that are designed to time-divisionally drive six or more signals lines.
Additionally, Japanese Laid-Open Patent Application No. P2001-109435A discloses a display device which drives two signal lines with a single amplifier, in which the write sequences of the pixels are switched for every vertical and/or horizontal scanning period. This technique allows the pixels experiencing increased changes in the drive voltages to be temporally and/or spatially scattered, thus eliminating vertical segments of uneven brightness.